Metal gate device with reduced oxidation of a high-k gate dielectric

ABSTRACT

Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/158,621, filed Jun. 21, 2005, entitled “METAL GATE DEVICE WITHREDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC” the entire contents ofwhich are hereby incorporated by reference herein.

BACKGROUND

1. Background of the Invention

MOS field-effect transistors with very thin silicon dioxide based gatedielectrics may experience unacceptable gate leakage currents. Formingthe gate dielectric from certain high-k dielectric materials, instead ofsilicon dioxide, can reduce gate leakage. When conventional processesare used to form such transistors, a silicon dioxide transition layermay form between the high-k dielectric and the substrate. The presenceof that transition layer may unfavorably contribute to the overallelectrical thickness of the gate dielectric stack.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional side view that illustrates the semiconductordevice of one embodiment of the present invention.

FIG. 2 is a cross sectional side view that illustrates additionalregions added to the substrate in some embodiments.

FIG. 3 is a cross sectional side view that illustrates the capping layerdeposited on the top surface of the gate stack, the first set of spacersand the substrate.

FIG. 4 is a cross sectional side view that illustrates a second set ofspacers formed on either side of the gate electrode.

FIGS. 5 a and 5 b are cross sectional side views that illustrate theformation of source/drain implant regions.

FIG. 6 is a cross sectional side view that illustrates the device ofFIG. 5 a after annealing of the source/drain implanted regions.

FIG. 7 is a cross sectional side view that illustrates the device afterremoval of portions of the capping layer.

FIG. 8 is a flow chart that summarizes a method according to anembodiment of the present invention.

FIG. 9 illustrates a system in accordance with one embodiment of thepresent invention.

DETAILED DESCRIPTION

In various embodiments, an apparatus and method relating to theformation of a substrate are described. In the following description,various embodiments will be described. However, one skilled in therelevant art will recognize that the various embodiments may bepracticed without one or more of the specific details, or with otherreplacement and/or additional methods, materials, or components. Inother instances, well-known structures, materials, or operations are notshown or described in detail to avoid obscuring aspects of variousembodiments of the invention. Similarly, for purposes of explanation,specific numbers, materials, and configurations are set forth in orderto provide a thorough understanding of the invention. Nevertheless, theinvention may be practiced without specific details. Furthermore, it isunderstood that the various embodiments shown in the figures areillustrative representations and are not necessarily drawn to scale.

Reference throughout this specification to “one embodiment” or “anEmbodiment” means that a particular feature, structure, material, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the invention, but do not denote that theyare present in every embodiment. Thus, the appearances of the phrases“in one embodiment” or “in an embodiment” in various places throughoutthis specification are not necessarily referring to the same embodimentof the invention. Furthermore, the particular features, structures,materials, or characteristics may be combined in any suitable manner inone or more embodiments. Various additional layers and/or structures maybe included and/or described features may be omitted in otherembodiments.

Various operations will be described as multiple discrete operations inturn, in a manner that is most helpful in understanding the invention.However, the order of description should not be construed as to implythat these operations are necessarily order dependent. In particular,these operations need not be performed in the order of presentation.Operations described may be performed in a different order than thedescribed embodiment. Various additional operations may be performedand/or described operations may be omitted in additional embodiments.

FIG. 1 is a cross sectional side view that illustrates the semiconductordevice of one embodiment of the present invention. In that semiconductordevice, a high-k gate dielectric layer 102 may be formed on substrate100, and a metal gate electrode 104 may be formed on the high-k gatedielectric layer 102. In the illustrated embodiment, there is aconductive gate layer 108, which may comprise doped polysilicon, on themetal gate electrode 104, although in other embodiments, the metal gateelectrode 104 may extend higher and the device may lack a dopedpolysilicon or other conductive gate layer 108 on the metal gateelectrode.

Substrate 100 may comprise any material that may serve as a foundationupon which a semiconductor device may be built. In this embodiment,substrate 100 is a silicon containing substrate. The substrate 100 maybe a bulk substrate 100, such as a wafer of single crystal silicon, asilicon-on-insulator (SOI) substrate 100, such as a layer of silicon ona layer of insulating material on another layer of silicon, or anothertype of substrate 100. The device formed on the substrate 100 may be atransistor in some embodiments. The device may be a planar transistor ona bulk substrate 100, a planar transistor on an SOI substrate 100, aFIN-FET transistor on a bulk substrate 100, a FIN-FET transistor on anSOI substrate 100, a tri-gate transistor on a bulk substrate 100, atri-gate transistor on an SOI substrate, or another type of transistoror other device.

The high-k gate dielectric layer 102 may comprise, for example, hafniumoxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, titanium oxide, tantalumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, and lead zinc niobate. Although a few examples of materials thatmay be used to form the high-k gate dielectric layer 102 are describedhere, the high-k gate dielectric layer 102 may be made from othermaterials that serve to reduce gate leakage in other embodiments.

In one embodiment of the present invention, high-k gate dielectric layer102 may be formed on the substrate 100 by an atomic layer chemical vapordeposition (“ALCVD”) process. In an ALCVD process, a growth cycle may berepeated until a high-k gate dielectric layer 102 of a desired thicknessis created. Such a growth cycle may comprise the following sequence inan embodiment. Steam is introduced into a CVD reactor for a selectedpulse time, followed by a purging gas. A precursor (e.g., anorganometallic compound, a metal chloride or other metal halide) is thenpulsed into the reactor, followed by a second purge pulse. (A carriergas that comprises nitrogen or another inert gas may be injected intothe reactor at the same time.)

While operating the reactor at a selected pressure and maintaining thesubstrate at a selected temperature, steam, the purging gas, and theprecursor are, in turn, fed at selected flow rates into the reactor. Byrepeating this growth cycle—steam, purging gas, precursor, and purginggas—multiple times, one may create a high-k gate dielectric layer 102 ofa desired thickness on the substrate 100. The pressure at which thereactor is operated, the gases' flow rates, and the temperature at whichthe substrate is maintained may be varied depending upon the applicationand the precursor that is used. The CVD reactor may be operated longenough to form the high-k gate dielectric layer 102 with the desiredthickness. In some embodiments, the high-k gate dielectric layer 102 maybe less than about 40 angstroms thick. In other embodiments, the high-kgate dielectric layer 102 may be between about 5 angstroms and about 20angstroms thick.

The high-k gate dielectric layer 102 may have a k-value higher thanabout 7.5 in some embodiments. In other embodiments, the high-k gatedielectric layer 102 may have a k-value higher than about 10. In otherembodiments, the high-k gate dielectric layer 102 may comprise amaterial such as Al₂O₃ with a k-value of about 12, or may comprise amaterial with a higher k-value than that. In other embodiments, thehigh-k gate dielectric layer 102 may have a k-value between about 15 andabout 25, e.g. HfO₂. In yet other embodiments, the high-k gatedielectric layer 102 may have a k-value even higher, such as 35, 80 oreven higher.

After forming the high-k gate dielectric layer 102 on the substrate 100,the metal gate electrode 104 may be formed on the high-k gate dielectriclayer 102. Metal gate electrode 104 may be formed using conventionalmetal deposition processes, e.g. CVD or PVD processes, by using ALCVD,or another suitable method, and may comprise any conductive materialfrom which metal gate electrodes may be derived. Materials that may beused to form n-type metal gate electrodes include: hafnium, zirconium,titanium, tantalum, aluminum, their alloys (e.g., metal carbides thatinclude these elements, i.e., hafnium carbide, zirconium carbide,titanium carbide, tantalum carbide, and aluminum carbide), andaluminides (e.g., an aluminide that comprises hafnium, zirconium,titanium, tantalum, or tungsten). Materials for forming p-type metalgate electrodes include: ruthenium, palladium, platinum, cobalt, nickel,and conductive metal oxides, e.g., ruthenium oxide. Alternatively, amid-gap metal gate material, e.g. stoichiometric titanium nitride ortantalum nitride, may be used in some embodiments.

In some embodiments, metal NMOS gate electrodes may have a workfunctionthat is between about 3.9 eV and about 4.2 eV. In some embodiments,metal PMOS gate electrodes may have a workfunction that is between about4.9 eV and about 5.2 eV. A metal gate electrode 104 that is formed on ahigh-k gate dielectric layer 102 may consist essentially of ahomogeneous metal layer. Alternatively, relatively thin n-type or p-typemetal layers (like those listed above) may generate the lower part ofthe metal gate electrode, with the remainder of the metal gate electrodecomprising another metal or metals, e.g., a metal that may be easilypolished like tungsten, aluminum, titanium, or titanium nitride.Although a few examples of materials for forming a metal gate electrodeare identified here, such a component may be made from many othermaterials, as will be apparent to those skilled in the art.

Additionally, while device may be an NMOS or PMOS device, other types ofdevices may be made within the scope of the present invention as well.For example, a silicon on insulator (SOI) or other type of device may bemade with mid-gap gate electrode materials, e.g. stoichiometric titaniumnitride or tantalum nitride, among other materials, rather than NMOS orPMOS gate electrode materials. In some embodiments, the material of themid-gap gate electrode 104 may have a workfunction between theworkfunctions of NMOS and PMOS gate electrode materials

There may be a set of first spacers 106 formed on either side of thegate electrode 104, high-k gate dielectric layer 102, and conductivegate layer 108. The spacers 106 may be formed of a material that issubstantially free of oxygen in some embodiments. For example, in anembodiment the set of first spacers 106 may comprise a carbon dopednitride, with 8-12% carbon and silicon nitride. In other embodiments,the set of first spacers 106 may comprise other materials.

In an embodiment, the device may be a transistor. There may be a thinoxide layer 110 on the substrate 100 beneath the gate stack 102, 104,108 and first set of spacers 106 in some embodiments. This thin oxidelayer 110 may be as thin as a monolayer of oxide in some embodiments.The thin oxide layer 110 may provide a potential path for oxygen totravel from an outer edge of the first set of spacers 106 furthest fromthe gate stack 102, 104, 108 to a region beneath the gate stack 102,104, 108. If oxygen reaches that region it may react with the substrate100 to form an unwanted thicker oxide beneath the gate stack 102, 104,108 and reduce the performance of the transistor.

FIG. 2 is a cross sectional side view that illustrates additionalregions 202 added to the substrate 100 in some embodiments. Theadditional regions 202 may be added in some embodiments but omitted inother embodiments. For example, when the device is a Fin-FET transistoror tri-gate transistor, there may be only a small amount of substrate oneither side of the gate stack 102, 104, 108. In such an embodiment, itmay be beneficial to add material to the substrate 100 by forming theadditional regions 202. In some embodiments, the additional regions 202may be added by epitaxy. In an embodiment, the additional regions 202may comprise the same material as the original substrate 100. Theadditional regions 202 may be considered portions of the substrate 100after formation of the additional regions 202. As shown in FIG. 2, theadditional regions 202 may have a height above the original substrate100 a distance away from the first set of spacers 106, but the thicknessof the additional regions 202 may decrease closer to the first set ofspacers 106. In some embodiments, such as when the device is a planartransistor, the additional regions 202 may be omitted.

FIG. 3 is a cross sectional side view that illustrates capping layer 302deposited on the top surface of the gate stack 102, 104, 108, the firstset of spacers 106 and the substrate, according to one embodiment of thepresent invention. In an embodiment, the capping layer 302 may be anoxygen barrier layer 302 that at least partially, if not completely,prevents oxygen from reaching a region 304 beneath the gate stack 102,104, 108. The capping layer 302 may seal the thin oxide layer 110 fromoxygen-containing structures and/or ambient oxygen in further processsteps, so may prevent the transport of oxygen by the thin oxide layer110 into the region 304 beneath the gate stack 102, 104, 108. Thisprevention of oxygen transport beneath the gate stack 102, 104, 108 mayat least partially prevent oxidation of the substrate 100, which couldresult in the formation of undesired oxide, such as silicon oxide,beneath the gate stack 102, 104, 108. Such an undesired oxide could beof a thickness enough to degrade the performance of the device if itsformation is not prevented. In an embodiment, the capping layer 302 maybe less than about 75 angstroms thick. In another embodiment, thecapping layer 302 may be about 50 angstroms thick or less. In anembodiment, the capping or oxygen barrier layer 302 may comprise anitride material, such as a carbon doped nitride, a stoichiometricsilicon nitride deposited in a low O₂-push fashion or a silicon carbide,although other materials may be used in other embodiments. The cappinglayer 302 may be substantially free from oxygen, so as not to serve as asource of oxygen that could be transported by the thin oxide layer tothe region 304 beneath the gate stack 102, 104, 108. In an embodiment,the capping layer 302 may be a conformal layer that covers the exposedsurfaces of the device. In an embodiment, the capping or oxygen barrierlayer 302 may be deposited by chemical or physical vapor deposition,although atomic layer deposition or other methods may be used asappropriate. The formation of the capping layer 302 may be performed inan ambient atmosphere with little or no oxygen.

FIG. 4 is a cross sectional side view that illustrates a second set ofspacers 402 formed on either side of the gate electrode 104, accordingto one embodiment. In an embodiment, the second set of spacers 402 maybe formed by depositing a thick layer of material over the device, thenetching portions of the layer away to form the second set of spacers402. In an embodiment, the second set of spacers 402 may comprise anoxygen-containing material such as a Bis(tert-butylamino)silane-basedsilicon oxide, a silicon oxynitride, or another material, depending onthe need to subsequently recess said second spacers following theself-aligned source/drain implant described below. As the capping layer302 may seal the thin layer of oxide 110 away from the layer of materialused to make the second set of spacers 402, the material used to makethe second set of spacers 402 may contain oxygen; the capping layer 302may prevent transport of oxygen from the material of the second set ofspacers 402 to the region 304 beneath the gate stack 102, 104, 108, andtherefore prevent formation of a thicker oxide layer 110.

FIG. 5 a is a cross sectional side view that illustrates the formationof source/drain implant regions 504 by implantation of ions 502, as isknown in the art. In the illustrated embodiment, the ions 502 areimplanted into the substrate 100 to form the source/drain implantedregions 504 through the capping layer 302 on the substrate 100.

FIG. 5 b is a cross sectional side view that illustrates anotherembodiment of the formation of source/drain implant regions 504 byimplantation of ions 502, as is known in the art. In the illustratedembodiment, portions of the capping layer 302 beyond the second set ofspacers 402 have been removed prior to ion implantation. The ions 502are implanted into the substrate 100 to form the source/drain implantedregions 504 without being implanted through the capping layer 302 on thesubstrate 100. The remaining portions of the capping layer 302 may besufficient to seal the thin oxide layer 110 from oxygen present instructures of the device and present in the ambient atmosphere duringfurther processing. Thus, as shown in FIGS. 5 a and 5 b, portions of thecapping layer 302 that do not function to seal the thin oxide layer fromsources of oxygen may be removed at various times during formation ofthe device in various embodiments.

FIG. 6 is a cross sectional side view that illustrates the device ofFIG. 5 a after annealing of the source/drain implanted regions 504 havebeen performed to form source and drain regions in the substrate 100, asis known in the art. The annealing process may be a high temperatureannealing process. During the annealing process, the capping layer 302may help prevent formation of an oxide under the gate electrode 104.Absent the capping layer 302, the high temperature of the annealingprocess may cause rapid formation of a thick layer of oxide beneath thegate stack 102, 104, 108, reducing the performance of the device.

FIG. 7 is a cross sectional side view that illustrates the device afterremoval of portions of the capping layer 302 that are exposed and notcovered by the second set of spacers 402. The removal may be done by awet etching process in one embodiment, although any suitable process maybe used to remove the exposed portions of the capping layer 302. Asstated above, this removal of portions of the capping layer 302 may bedone at other times during processing of the device rather thanfollowing anneal. Following anneal and removal of portions of thecapping layer 302, additional steps such as silicidation may beperformed to finish fabricating the device.

FIG. 8 is a flow chart 800 that summarizes a method according to anembodiment of the present invention. A gate stack of a device, such asgate stack 102, 104, 108 shown in FIG. 1, may be formed 802. A cappinglayer, such as capping layer 302 of FIG. 3, may be formed 804, sealing aregion under the gate stack from oxygen. For example, region 304 of FIG.3 is sealed by capping layer 302 to prevent oxygen from beingtransported by the thin oxide layer 110 under the gate stack 102, 104,108 and forming a thick oxide layer that would degrade deviceperformance. Processes at high temperature or processes that involveoxygen (as part of an ambient atmosphere or part of the material of astructure) may then be performed 806. Since the under gate region issealed by the capping layer 302, oxygen may be mostly or entirelyprevented from being transported to the under gate region during theseprocesses. Thus, reaction of oxygen with the substrate beneath the gateand formation of a thick oxide layer beneath the gate may be avoided,which may prevent degradation of the performance of the device.

FIG. 9 illustrates a system 900 in accordance with one embodiment of thepresent invention. One or more devices formed with the capping layer 302as described above may be included in the system 900 of FIG. 9. Asillustrated, for the embodiment, system 900 includes a computing device902 for processing data. Computing device 902 may include a motherboard904. Coupled to or part of the motherboard 904 may be in particular aprocessor 906, and a networking interface 908 coupled to a bus 910. Achipset may form part or all of the bus 910. The processor 906, chipset,and/or other parts of the system 900 may include one or more deviceswith the capping layer 302.

Depending on the applications, system 900 may include other components,including but are not limited to volatile and non-volatile memory 912, agraphics processor (integrated with the motherboard 904 or connected tothe motherboard as a separate removable component such as an AGP orPCI-E graphics processor), a digital signal processor, a cryptoprocessor, mass storage 914 (such as hard disk, compact disk (CD),digital versatile disk (DVD) and so forth), input and/or output devices916, and so forth.

In various embodiments, system 900 may be a personal digital assistant(PDA), a mobile phone, a tablet computing device, a laptop computingdevice, a desktop computing device, a set-top box, an entertainmentcontrol unit, a digital camera, a digital video recorder, a CD player, aDVD player, or other digital device of the like.

Any of one or more of the components 906, 914, etc. in FIG. 9 mayinclude one or more devices with the capping layer 302 as describedherein. For example, a transistor formed with the capping layer 302 maybe part of the CPU 906, motherboard 904, graphics processor, digitalsignal processor, or other devices.

In an embodiment, the device may be a semiconductor device including asubstrate, a thin oxide layer on the substrate, a high-k gate dielectriclayer on the thin oxide layer, a metal gate electrode on the high-k gatedielectric layer, and a capping layer that is substantially free ofoxygen and substantially seals the thin oxide layer from structures thatcomprise oxygen. The device may also have a first set of spacers oneither side of the metal gate electrode and a second set of spacers oneither side of the first set of spacers, wherein the capping layer isbetween the first set of spacers and the second set of spacers. Thesecond set of spacers may have a bottom surface and the capping layermay extend beneath the bottom surface of the second set of spacers. Thefirst set of spacers may have a bottom surface and the thin oxide layermay extend beneath the bottom surface of the first set of spacers. Thecapping layer may be on the sides of the first set of spacers and may beon the substrate extending away from the sides of the first set ofspacers for a distance.

The foregoing description of the embodiments of the invention has beenpresented for the purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. This description and the claims following include terms, suchas left, right, top, bottom, over, under, upper, lower, first, second,etc. that are used for descriptive purposes only and are not to beconstrued as limiting. For example, terms designating relative verticalposition refer to a situation where a device side (or active surface) ofa substrate or integrated circuit is the “top” surface of thatsubstrate; the substrate may actually be in any orientation so that a“top” side of a substrate may be lower than the “bottom” side in astandard terrestrial frame of reference and still fall within themeaning of the term “top.” The term “on” as used herein (including inthe claims) does not indicate that a first layer “on” a second layer isdirectly on and in immediate contact with the second layer unless suchis specifically stated; there may be a third layer or other structurebetween the first layer and the second layer on the first layer. Theembodiments of a device or article described herein can be manufactured,used, or shipped in a number of positions and orientations. Personsskilled in the relevant art can appreciate that many modifications andvariations are possible in light of the above teaching. Persons skilledin the art will recognize various equivalent combinations andsubstitutions for various components shown in the Figures. It istherefore intended that the scope of the invention be limited not bythis detailed description, but rather by the claims appended hereto.

1. A semiconductor device, comprising: a substrate; a high-k gatedielectric layer on the substrate; a metal gate electrode on the high-kgate dielectric layer; and a capping layer that is substantially free ofoxygen and substantially seals a region between the high-k gatedielectric layer and the substrate from structures that comprise oxygen.2. The device of claim 1, further comprising: a first set of spacers oneither side of the metal gate electrode; a second set of spacers oneither side of the first set of spacers; and wherein the capping layeris between the first set of spacers and the second set of spacers. 3.The device of claim 2, wherein the second set of spacers have a bottomsurface and the capping layer extends beneath the bottom surface of thesecond set of spacers.
 4. The device of claim 1, further comprising athin oxide layer between the high-k gate dielectric layer and thesubstrate and a first set of spacers on either side of the metal gateelectrode, wherein the first set of spacers have a bottom surface andthe thin oxide layer extends beneath the bottom surface of the first setof spacers.
 5. The device of claim 1, wherein the capping layercomprises a nitride material.
 6. The device of claim 5, wherein thecapping layer has a thickness below about 75 angstroms.
 7. The device ofclaim 5, wherein the capping layer comprises a material selected fromthe group consisting of 8-12% carbon-doped silicon nitride,stoichiometric silicon nitride and silicon carbide.
 8. The device ofclaim 2, wherein the second set of spacers have a bottom surface and thecapping layer extends beneath the bottom surface of the second set ofspacers.